A low-power CMOS neural amplifier with amplitude measurements for spike sorting

Integrated, low-power, low-noise CMOS neural amplifiers have recently grown in importance as large microelectrode arrays have begun to be practical. With an eye to a future where thousands of signals must be transmitted over a limited bandwidth link or be processed in situ, we are developing low-power neural amplifiers with integrated pre-filtering and measurements of the spike signal to facilitate spike-sorting and data reduction prior to transmission to a data-acquisition system. We have fabricated a prototype circuit in a commercially-available 1.5 /spl mu/m, 2-metal, 2-poly CMOS process that occupies approximately 91,000 square /spl mu/m. We report circuit characteristics for a 1.5 V power supply, suitable for single cell battery operation. In one specific configuration, the circuit bandpass filters the incoming signal from 22 Hz to 6.7 kHz while providing a gain of 42.5 dB. With an amplifier power consumption of 0.8 /spl mu/W, the rms input-referred noise is 20.6 /spl mu/V.