A CMOS high-speed multistage preamplifier for comparator design

A new multistage preamplifier with offset reduction for use in high-speed comparator is presented. The proposed circuit is based on the cascade of the modified input offset storage amplifiers and the output offset storage amplifier in pipeline arrangement. Not only does the topology maintain a good input common-mode range, it exhibits faster speed due to the reduced capacitive loads. Using AMS 0.35 /spl mu/m CMOS process model, the simulation result has shown that the new preamplifier has achieved a settling time of 3.5 ns at 1% accuracy for a transient step of 400 mV, which is faster than the conventional works at identical power consumption.