Built-in self-test and repair (BISTR) techniques for embedded RAMs

High-density and high capacity embedded memories are important components for successful implementation of a system-on-a-chip. Since embedded memory cores usually occupy a large portion of the chip area, they will dominate the manufacturing yield of the system chips. In this paper, a built-in self-test and repair (BISTR) approach is proposed for semiconductor memories with 1-D redundancy (redundant rows) structures. The memory rows are virtually divided into row blocks and reconfiguration is performed at the row block level instead of the traditional row level. That is, the virtual divided word line (VDWL) concept is used for repairing of memory cores. The hardware overhead is almost negligible. An experimental chip is implemented and shows a low area overhead - about 3.06% for a 256 /spl times/ 512 SRAM with 4 spare rows. We also compare the repair rate of our approach with previous memory repair algorithms. It also concludes that our approach improves the repair rate significantly.