Radio frequency digital-to-analog converter

Dynamic performance of high-speed high-resolution digital-to-analog converters (DACs) is limited by distortion at the data switching instants. Inter-symbol interference (ISI), imperfect timing synchronization, and clock jitter are all culprits. A DAC output controlled by an oscillating waveform is proposed to mitigate the effects of switching distortion and clock jitter. This architecture has the additional benefit of mixing the DAC impulse response energy to a higher frequency, allowing a high-frequency image of the input to be used as the output. This has the potential for better noise performance and power and hardware savings relative to a conventional DAC+mixer architecture. A narrow-band sigma-delta (/spl Sigma//spl Delta/) DAC with eight unit elements is chosen to demonstrate the radio frequency digital-to-analog converter (RF DAC) concept in a 1.8-V 0.18-/spl mu/m CMOS technology. Measured single-tone SFDR is -75 dBc, SNR is 53 dB, and two-tone IMD3 is -70.8 dBc for a 17.5-MHz band centered at 942 MHz. SNR performance is shown to have the predicted dependence on the phase alignment of the data clock and oscillating pulse.