Low-current blocking temperature writing of double-barrier MRAM cells

A magnetic random access memory (MRAM) cell architecture is fabricated where the pinned layer is reversed by heating above a reduced blocking temperature with a current pulse crossing the junction, and cooled under an external applied field (word line), minimizing half-select switching of nonaddressed bits. In order to improve Joule heating and increase breakdown voltage, a double barrier structure was used, with a common antiferromagnetic layer (60 /spl Aring/ MnIr), two pinned 30 /spl Aring/ CoFe layers, and two free layers incorporating nano-oxide structures. Pinned layer writing allows the definition of a three-state memory, requiring however destructive read-out. The pinned layer blocking temperature was reduced to 120/spl deg/C. TMR of 28% was achieved with resistance /spl times/ area products /spl sim/280 /spl Omega//spl times//spl mu/m/sup 2/. The double barrier presents a dc breakdown voltage of 1.8 V, but can sustain higher voltages under short current pulses (3.1 V at 10 ns pulses). A 10 ns current pulse of 9 mA//spl mu/m/sup 2/ is sufficient to heat the double barriers junctions above the blocking temperature and induce pinned layer switching. Barrier reliability was tested and junction properties were found to be not altered for 2.4/spl times/10/sup 10/, 10 ns width, 9.25 mA//spl mu/m/sup 2/ thermal write cycles.