A flow graph analysis algorithm for a data driven reconfigurable parallel pipelined computer architecture

A flow graph analysis algorithm (FGAA) and its proof, utilized in conjunction with a data-driven reconfigurable parallel-pipelined computer architecture system, are presented. The architectural system was developed such that any real-time data-driven application describable as a data-flow graph could be executed on the system. A requirement for utilization of the architectural system is an ability to describe the structure and linkages of the data-flow graph to the operating system (OS). This requirement is accomplished by a data-flow language and interpreter, which is described. A second requirement is that the OS must have the capability of algorithmically assigning processes of a flow graph to specific computing elements (CEs) of the architecture, in a manner that assures that real-time timing constraints from input node to output node of any data flow graph can be met. A third requirement is that processes must be assigned to CEs in a manner which minimizes system resources. The FGAA was developed to meet these latter requirements.<
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