Outline of the ultra fine grained parallel processing by FPGA

This work addresses a scheme to extract parallelism from a C-level program and implement parallel calculation units on a FPGA by adding parallel directives for C-level design tool. FPGA (field programmable gate array) is a chip that can be programmed their internal circuit by user dynamically. Hardware circuit such as the FPGA runs in parallel, because each sub-circuit executes their function independently. Thus, if we implement software algorithms, like numerical simulations or text processing written by C-language, on a FPGA as a parallel circuit, operator level ultra fine grained parallel processing can be achieved. However, conventional C-level design tool for hardware description aims co-design for software and hardware and they can not synthesize parallel circuit. This research propose a preprocessor to implement highly parallel hardware circuit on a FPGA that analyzes parallelism in a given C-program and automatically unrolls loop or inserts parallel directives for a C-level design tool. Compiling and executing the parallelized C-code, the given program will be accelerated on a FPGA board.