Parallel architecture for VLSI implementation of a 2-dimensional discrete cosine transform for image coding

A new efficient parallel architecture is presented for high-speed two-dimensional discrete cosine transform (DCT) for image data compression with a block size of 8*8 picture elements. This circuit is applicable in advanced television and HDTV systems working at video sampling-rate up to 80 MHz and can be realized in CMOS technology as a single VLSI component.<
>