Design considerations, of differential inductors in CMOS technology for RFIC

The differential (symmetric) inductor is useful for its higher Q factor and smaller area than a single-end inductor in silicon-based RFIC. The limitations are the inductance value and the inductor track width. Large inductance or track width often results in too high overall capacitances and too large an area. This paper addresses the issues of present differential inductor limitations and discusses a new type of differential inductor using multi-layer inter-leaf windings to overcome the present limitations. Significant area reduction is found. The designs based on the full-wave integral-equation simulation are intended for a six-metal layer 0.18 /spl mu/m CMOS technology, but it is also applicable to other silicon-base technologies. New compact high-performance differential inductors are fabricated and tested to validate the designs.