A novel D-latch in multiple-valued semi-floating-gate recharged logic

In this paper, we present several different proposals for implementing a multiple-valued (MV) semi-floating-gate (SFG) D-latch. This paper aims to illustrate the advantages and disadvantages of each approach. Measurements from a fabricated chip in a 0.6 /spl mu/m CUP process is included for verifying the detailed arguments.