Development of organic flip chip packaging technology for nanometer silicon incorporating copper metallization and low-k dielectric

This paper describes the design, development, and qualification of an organic flip chip packaging technology for 110 nm silicon, incorporating Cu metallization and low-k dielectric (Gflx/spl trade/ silicon technology) at LSI Logic. This package technology enables signal placement all over the die, thereby increasing the signal I/O count by as much as 80% over peripheral flip chip packages. The package design also incorporates a novel ball assignment scheme that enables reduction in the total layer count required for escaping signals on the PCB. Results of PCB routing studies for various package body sizes and pin counts are presented. The package design also incorporates discrete chip capacitors to reduce SSO noise by up to 50%. Critical to the success of this package is mechanical stress modeling. Results of critical die-underfill stresses and assembly material optimization for Cu/low-k silicon are summarized. Finally, the paper presents the results of extensive JEDEC-standard qualification tests that were successfully passed by the package as well as the results of board level reliability tests conducted per IPC-9701 guidelines. As a result of the qualification, LSI Logic offers an organic flip chip package family up to 52.5 mm body size, large die Cu/low-k silicon and 2597 pin count to the industry.