A novel joint-in-via, flip-chip chip-scale package

It is believed that the slower-than-expected adoption of flip-chip (FC) packages is due to the lagging advancement in substrate designs and technologies with front-end processes. This lag has also resulted in the need for a costly redistribution layer (RDL), which fans out the die pads to meet the substrate design rule. This paper reviews the photographic metallization limitation of organic substrates and proposes an innovative joint-in-via architecture using existing substrate technologies to improve the pad pitch resolutions. The joint-in-via architecture consolidates the landing pads, the micro-vias, and the flip-chip joint into one common element, thereby saving valuable substrate real estate for high-density routing. It has been successfully conceptualized on a flex laminate at a pad pitch of 70 /spl mu/m and a receiving pad size of 50 /spl mu/m, potentially enabling the removal of the RDL layer for packaging. Robustness in flip-chip assembly is improved by the joint-in-via architecture because it prevents solder bridging and allows the use of existing packaging infrastructure. A new flip-chip, chip-scale package (FC-CSP) has evolved with the implementation of the joint-in-via architecture. With material optimization, the FC-CSP passes standard reliability tests, further demonstrating the robustness of the joint-in-via technology.