High-performance, four-layer, wire-bonded, plastic ball grid array package for a 10 Gbps per lane backplane SerDes transceiver

A high-performance package design was required for a SerDes-to-SerDes Mux chip for backplane applications using eight 1.0-3.125 Gbps lanes on the system side and four 1.0-10.0 Gbps lanes on the backplane side. Cost and thermal targets required that this chip be built with wirebond assembly in a four-layer, 19/spl times/19mm 324 ball Plastic Ball Grid Array. Preliminary simulations were used to define package layout rules. Final 3-D simulations on the completed design showed that at 3.125GHz return loss was less than -20dB. At 10GHz, insertion loss was less than -1.0dB and crosstalk less than -50dB. Thermal simulations showed a thermal resistance of 11/spl deg/C/W using thermal vias, 1 m/s airflow, 2oz Cu power planes, a heat spreader, and 0.5mm solder balls.