A novel VLSI architecture for multidimensional discrete wavelet transform

A novel VLSI architecture for multidimensional discrete wavelet transform (mD DWT) based on a systolic array is proposed. We divide the input mD image data into 2/sup m/ independent data streams, and then simultaneously pipeline them into a multi-filter chip, and finally obtain 2/sup m/ samples which are from different DWT subbands per clock cycles (ccs). The proposed architecture performs a decomposition of an N/sub 1//spl times/N/sub 2//spl times/.../spl times/N/sub m/ image in about N/sub 1/N/sub 2/...N/sub m//(2/sup m/-1) ccs and requires relatively lower hardware cost than previous architectures. Besides, the advantages of the proposed architecture include very simple hardware complexity, regular data flow and low control complexity.