Scaling of thermal stresses in passivated nano-interconnects

Much work has been done in the approximation of the stress state of microelectronics interconnects-on-chips. The thermally induced stresses in passivated interconnects are of interest as they are used as input in interconnect reliability failure models (stress-driven void growth, electromigration driven void growth). The typically used classical continuum mechanics and physics is, however, intrinsically size-independent. This is in contradiction to the physical fact that at the size-scale of a few nanometers, the elastic state is size-dependent and a departure from classical mechanics is expected. In this work, we address the various physical causes (and the affiliated mathematical modeling) of the size-dependency of mechanical stresses in nano-interconnects. In essence, we present scaling laws for mechanical stresses valid for nano-sized interconnect.