Design and application of CMOS bulk input scheme

This work presents CMOS bulk input differential logic (BIDL) circuits. The bulk input scheme is applied to enable bulk terminals to receive signals. A boost circuit is employed to the bulk terminal of an input device. A multiple-input boost circuit is also developed to improve the flexibility of logic design. A current latch sense amplifier is used to generate a pair of full-swing output signals without dc power dissipation. The devices in the differential logic network are connected in parallel, leading to a low parasitic resistive and capacitive load. The BIDL has better speed and power performance than conventional differential logic circuits. The flexibility of the logic design is greatly improved. The BIDL is applied to a divide-by-128/129 frequency synthesizer using a 0.25-/spl mu/m CMOS process. Measurement results of the test chip indicate that the operating frequency is 2 GHz at a supply voltage of 2.5 V.