Multi-level programming of NOR flash EEPROMs by CHISEL mechanism

Multi-level (ML) storage is becoming an important option to achieve high-density flash EEPROMs. This is done by storing different amount of charges in the floating gate (FG) to reliably distinguish different levels and treating these levels as different combination of bits. Since large amount of charges need to be stored in FG for ML operation, faster programming is required so that the overall writing speed is not compromised. In addition, this needs to be done without much increase in programming power. Recently, CHannel Initiated Secondary ELectron (CHISEL) injection was shown as an excellent low power and fast programming scheme for NOR flash EEPROMs. The performance, scalability and reliability of CHISEL were demonstrated for bi-level programming. However to the best of our knowledge, very few studies have focused on the feasibility of using CHISEL mechanism for ML programming. This paper demonstrates the performance and reliability of flash cells under ML CHISEL programming operation. Program transients show excellent self-convergence leading to accurate V/sub T/ control. Six different bitcell doping schemes were studied and optimized doping is identified based on their program and drain-disturb performance. Cycling endurance was studied on the optimized bitcell. Programmed VT levels show very little degradation, program transients retain their self-convergence, program/disturb margin remains within limit while only the erased VT level shows some degradation after 100K cycling. The impact of bitcell scaling on the performance and reliability of ML CHISEL programming is also explored.