Design and implementation of a parameterizable LDPC decoder IP core

This paper presents a design methodology that quickly enables the design and implementation of a fully parallel log-domain LDPC decoder based on any parity check matrix. A simulation method to perform an analysis of an arbitrary LDPC code is presented and then extended to predict the actual performance of the final hardware implementation. The design trade-offs due to parameterizable terms such as message resolution and approximation of the log functions are discussed. Finally using the presented design methodology an IP core is generated (using a randomly chosen parity check matrix H). Results for this IP core are presented for an ASIC implementation using a 0.35 /spl mu/m CMOS technology.