Hot-carrier induced degradation of offset gated polysilicon TFTs

Hot-carrier effects are investigated in offset gated polysilicon thin-film transistors of channel length L = 10 /spl mu/m and offset length /spl Delta/L = 0.5 and 1 /spl mu/m, and compared with those of self-aligned devices. The gate and drain bias conditions for maximum device degradation were determined from substrate current measurements. In offset gated devices, the experimental data show that the threshold voltage and the on-state current degrade exhibiting a "staircase-like" behavior with stress time. The results are explained in terms of grain boundary trap filling, with electrons generated by impact ionization in successive small offset regions from the drain end.