Design and modeling of on-chip electrostatic discharge (ESD) protection structures

Electrostatic discharge (ESD) is a critical reliability concern for microchips. This paper presents a computer-aided design tool for ESD protection design and applications. Specifically, we develop an improved and robust MOS model and implement such a model into the industry standard Cadence SPICE for ESD circuit simulation. Experimental data measured from the transmission line pulsing (TLP) technique and human body model (HBM) tester are included in support of the model.