Multi-user FPGA co-simulation over TCP/IP

FPGA co-simulation of an IP core is an important design flow step in IP and system development. In this paper, we discuss how, with Xilinx's system generator for DSP 3.1 (XSG), it is possible for multiple-users to hardware co-simulate IP cores over any distance via TCP/IP, sharing only one FPGA board resource. The hardware co-simulation strategy is mutually exclusive in that only one user at any one time can hardware co-simulate on the FPGA board. We demonstrate this with the use of two encryption cores, Camellia and AES-128 (advanced encryption standard), which have both been generated using the block-based tool. The sharing of the FPGA board is handled with a set of Matlab function commands.