Advanced yield enhancement methodology for SoCs

A yield simulator utilizing the extracted critical area and a SoC yield management system has been developed. This system drastically improved accuracy of SoC yield prediction and successfully extracted the critical areas of all layers of 0.18 /spl mu/m SoCs in approximately one hour. For yield prediction, we have thus far extracted critical areas of over 150 SoCs since the 0.18 /spl mu/m nodes, and performed analysis of yield-loss factors. There are two factors that affect the device yield: field defects and product-inherent parametric failure. The yield calculated on the basis of critical areas is a prediction derived considering only field defects. It has been confirmed that SoCs failed to achieve the prediction had product-inherent parametric problems. The new system allows us to determine early in the development cycle whether or not a SoC has any inherent problems. The new system helps to quickly identify the root cause of a yield loss and reduce the time required to obtain yield improvement. Based on the experience of analyzing many SoC products, we have acquired design-for-manufacturing (DFM) expertise for improving yields for new and next-generation products.