Optimizing pattern fill for planarity and parasitic capacitance

In integrated circuit manufacturing with multi-level interconnect, it is important to have a planar surface preceding the next layer to avoid topography-induced patterning failure. In this paper, we describe a method for optimizing the use of pattern fill for planarity of CMP processing against the parasitic capacitive effects generated by such fill. Results applying this methodology on a seven metal product set are used to demonstrate its effectiveness.