Trimming of hard-masks by gaseous Chemical Oxide Removal (COR) for sub-10 nm gates/fins, for gate length control and for embedded logic

A method for formation and control of silicon gates or fins uses trim of a hard mask by a new gaseous oxide etch. The method decouples final feature size from lithography and from the RIE resist trim/oxide mask open processes. Logic blocks with two separately controlled gate lengths and dielectric thicknesses are embedded on chip. COR control has achieved final size sprads of 1 to 2 nm using measurements from either the factory CDSEM or from a scatterometer integrated on the process tool.