A bi-directional current-mode CMOS multiple valued logic memory circuit

A bidirectional current-mode multiple-valued logic (MVL) latch circuit realized in a standard 2- mu m polysilicon gate CMOS process is presented. The circuit accepts and quantizes a bidirectional input current during the setup clock phase and latches the quantized input during the hold clock phase. Characteristics of fully integrated prototypes realized on a CMOS test chip are presented. Using logical current increments of only 10 mu A, the bidirectional current-mode MVL latch's setup and hold time has been determined to total approximately 44 ns. The input/output propagation delay for transitions between adjacent states has been determined to be approximately 50 ns at these low current levels.<
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