Effect of metal layout design on passivation crack occurrence using both experimental and simulation techniques

Thermo-mechanical reliability is one of the concerns for semiconductor developments due to miniaturization, introduction of new materials, and higher application temperatures. FE modeling techniques are developed to predict the effect of IC interconnect metal designs on the thermo-mechanically-induced cracking of passivation layers. Experimental techniques on specially designed IC packages are developed to verify the predicted passivation cracks. With the verified 2D and 3D models, various simulations are performed and it is established that delamination of the IC/compound interface is a key trigger for passivation cracking. When delamination is present, crack occurrence is found to depend on the metal layout and location on the IC. Optimizing the metal layout design can even prevent passivation cracks. By combining efficient and accurate simulations with a limited number of experiments, passivation cracks can be quantitatively predicted prior to physical prototyping.