Parallel and pipeline processing for prioritized buffer management in photonic packet switches

We investigate a mechanism of high-speed buffer management for output-buffered photonic packet switches. In this paper we design a parallel and pipeline processing architecture to support prioritized buffer management. We propose a prioritized method which is suitable to parallel processing, by extending traditional partial buffer sharing. Packet loss probability in this method is almost the same as that of the traditional one. However, our design using O(NlogN) processors provides N times as much throughput as the traditional method in simple round-robin scheduling, where N is the number of ports of the packet switch. We show the feasibility of an FPGA-based buffer manager supporting 128/spl times/40 Gbit/s photonic packet switches.