Wavefront array processor for video applications

A single-chip MIMD wavefront array processor for video applications is presented. The processor topology is an array of individually programmable mesh-connected cells; processors may be cascaded indefinitely in one or two dimensions. 12-b word width, superscalar RISC cell architecture, and the 125-MHz clock rate are tailored toward the requirement of digital video signal processing. The processor executes statically scheduled data flow programs, propagating data through the array in a wavefront-like manner. The processor is implemented in 0.8- mu double-metal CMOS. It has 1.2 million transistors, a chip area of 150 mm/sup 2/, a pin count of 124, and a maximum power dissipation of 8 W.<
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