An approach to 150 K gate low power ECL cell based integrated circuits

A technology and a design system for implementing VLSI ECL circuits with 50 to 150 K gates is described. The technology provides high-density ECL logic and BiCMOS RAMs, while the design system avoids many of the hand checks previously required for successful ECL designs. System design considerations, standard cell based design methodology, design verification, and process technology are outlined.<
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