A novel frequency compensation technique for two-stage CMOS operational amplifiers

In this paper, a novel compensation technique for two-stage CMOS operational amplifiers (op-amps) is presented. This method employs a smaller total capacitance compared to that of the traditional-compensation approaches with similar frequency response. As this capacitor is not placed in the path of the signal, the large signal settling behavior and so the total settling time of the op-amp is improved. HSPICE simulations reveal that the proposed approach, compared to cascode-compensated counterpart, would reduce the total compensation capacitor and the settling time as high as 36% and 10%, respectively.