A 1.5-V 12-bit 75M-samples/s fully-differential low-power sample-and-hold amplifier in 0.25-/spl mu/m CMOS

The most power-hungry block in a pipelined analog-to-digital converter is the front-end sample-and-hold amplifier. When the sampling rate or the resolution is increased or the supply voltage is scaled down, the power is increased. In this paper, several approaches have been used to reduce the power consumption in low-voltage fast-settling operational amplifiers used for SHA. These techniques include the cascode-Miller compensation, utilizing a new class-AB output stage and a novel simple optimum allocation of settling time parameters. Design considerations for a 1.5-V very-low-power operational amplifier merging these techniques are addressed. HSPICE simulation results of the circuit in a 0.25-/spl mu/m CMOS process confirm the effectiveness of the approaches to considerably reduce the power consumption in the sample-and-hold amplifier.