Building blocks for a 100 MS/s, 10-b, 1.8 V CMOS cascaded folding & interpolating A/D converter

This paper describes building blocks of an A/D converter, based on the folding and interpolation techniques, for mobile and wireless telecommunication applications. The differential difference technique is used to double the dynamic input range and relax the circuit design for low voltage applications. The blocks are designed in a standard 1.8 V 0.18 /spl mu/m CMOS technology. The maximum sampling rate of the converter is 100 MS/s and the differential input voltage range is 2 V peak-peak.