Analog CMOS implementation of a multilayer perceptron with nonlinear synapses

A neurocomputer based on a high-density analog integrated circuit developed in a 3 mu m CMOS technology has been built. The 1.6 mm*2.4 mm chip contains 18 neurons and 161 synapses in three layers, and provides 16 inputs and 4 outputs. The weights are stored on storage capacitors of the synapses. A formalization of the error back-propagation algorithm which allows the use of very small nonlinear synapses is shown. The influence of offset voltages in the synapses on the circuit performance is analyzed. Some experimental results are reported and discussed.<
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