Scalable FPGA architectures for LMMSE-based SIMO chip equalizer in HSDPA downlink

In this paper, scalable FPGA architectures for the LMMSE-based chip-level equalizer in HSDPA downlink receivers are studied. An FFT-based algorithm is applied to avoid the direct matrix inverse by utilizing the block-Toeplitz structure of the correlation matrix. A pipelined-multiplexing-scheduler (PMS) is designed in the front-end to achieve scalable computation of the correlation coefficients. Very efficient VLSI architectures are designed by investigating the multiple level parallelism and pipelining with a precision-C based high-level-synthesis (HLS) design methodology. A 1/spl times/2 single-input-multiple-output (SIMO) downlink receiver is designed and integrated in the HSDPA prototype system with Xilinx Virtex-II XC2V6000 FPGAs. The design demonstrates more area/time efficiency by achieving the best tradeoffs between the usage of functional units and real-time requirements.