Congestion driven placement for VLSI standard cell design

The sub-micron regime has caused the interconnect delay to become a critical determiner of circuit performance. As a result, circuit placement is starting to play an important role in today's high performance chip designs. In addition to wirelength optimization, the issue of reducing excessive congestion in local regions such that the router can finish the routing successfully is becoming another important problem. In this paper, a post-processing congestion reduction technique is implemented and incorporated into the flat and hierarchical placement. Results obtained show that the congestion-driven placement approach reduces the congestion by about 51% for flat designs and 37% for hierarchical designs with a slight increase in wirelength.