An effective bus-based arbiter for processors communication

Multiprocessor system is made up of two or more main processing elements with similar capabilities running under a single operation system, and the processing elements communicate and cooperate with each other when data or control dependency. We discuss how to implement an affective multiple buses arbiter for the multiprocessor system. The arbitration of bus is based on two-stage arbitration logic control in interprocessor communication network. For the performance comparison, we analyze the message-transmission rate among processors for the proposed arbiter and the crossbar-based ones.