Yield optimization with energy-delay constraints in low-power digital circuits

As circuit parametric variations aggravate in advanced technology, yield emerges as an important figure-of-merit in circuit design. Based on a 130 nm technology, the yield-energy-delay tradeoffs in low-power circuit optimization are investigated. Using a log-normal statistical model, Monte-Carlo analyses are performed on typical circuit examples, including an inverter chain, NAND gate, and 4-bit adder. While energy reduction can be effectively achieved by tuning supply voltage (V/sub dd/), threshold voltage (V/sub th/), and device width (W), circuit yield degrades during this process. On the other hand, it is observed that performance variability is relatively insensitive to circuit topology and device length (L). Design guidelines for optimizing yield in the presence of parametric variations and energy-delay constraints are proposed.