Comparative analysis and parameter extraction of enhanced waffle MOSFET

Unlike the traditional layout strategy in which large size transistors were fabricated by increasing the number of parallel polysilicon gates, waffle MOSFET with a novel structure is introduced due to its excellent expansibility and area efficiency. In this work a compact waffle MOSFET using an enhanced waffle-layout strategy is presented. Comparisons are made on two different layout implementations of wide transistors with the same dimensions using a standard 0.35-/spl mu/m CMOS technology. With the proposed accurate model suitable to waffle MOSFET the small signal parameters are extracted and the experimental results demonstrate the benefits of waffle layout without any extra processing cost.