A polysilicon hard-mask/spacer process for sub-0.5 micron ULSI contacts

A contact formation process for fabricating sub-0.5- mu m contacts is proposed. By using a thin polysilicon layer and a spacer as the hard mask, the contact process bias can be reduced by as much as 0.4-0.5 mu m. The feasibility of this contact technology for ULSI applications is demonstrated by low contact resistivity (<5*10/sup -8/ Omega -cm/sup 2/) and well-behaved sub-0.5- mu m MOSFET devices.<
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