A mixed parallel neural networks computing unit implemented in FPGA

A FPGA implementation architecture of neural network (NN) computing unit is proposed in this paper. In the computing unit, link parallelism is designed between the input layer and middle layer of NN; neuron parallelism is designed between the middle layer and output layer. Moreover, the method of hardware implementation of the sigmoid function of NN is improved and a new method for weight locating in computing unit is proposed, which can simply the implementation of the NN greatly.