CMOS-compatible lateral bipolar transistor for BiCMOS technology. I. Modeling

A CMOS-compatible lateral bipolar transistor having neither an epitaxial layer nor n/sup +/-buried layers is proposed. The simulation indicates that the BiCMOS gate delay time shows a weak dependence on the metallurgical base width W/sub B/, (and hence on f/sub Tmax/, since f/sub T/ varies as 1/W/sub B//sup 2/) and strong dependence on the effective base width W/sub B(eff)/, where W/sub B(eff)/ nearly equals the distance between the emitter and the n/sup +/ collector, d/sub E-C/. This is because bipolar transistors in BiCMOS circuits are operated in high-level injection during the switching transient. Therefore, it is possible to build a high-speed BiCMOS gate using lateral bipolar devices with short d/sub E-C/. The transistor has a structure similar to that of an n-channel MOSFET. The emitter and collector are formed simultaneously and self-aligned to a polysilicon base electron like the source and drain in a MOSFET.<
>