A novel polysilicon gate engineering by laser thermal process for high performance sub-40 nm CMOS devices

A novel polysilicon gate engineering by laser thermal process (LPT) is developed to minimize the gate depletion even under low temperature SD-RTA and applied to sub-40 nm CMOS devices. BEOL process is optimized to suppress dopant deactivation. SD-RTA technique is developed to supress dopant dose loss for the maximization of the merit of LTP.