Low temperature MOSFET technology with Schottky barrier source/drain, high-K gate dielectrics and metal gate electrode

In this paper, we demonstrate a bulk SSDTs (Schottky barrier S/D) with CVD HfO/sub 2/ high-k dielectric, PVD HfN/TaN metal gate and PtSi (for PMOS) and DySi/sub 2-x/ (for NMOS) silicide source/drain using a low temperature process. Surface removing, cleaning, dipping and silicidation processes are carried out at highest temperature of 420/spl deg/C for 1h after a high-k gate stack formation. The process can be easily extended to UTB-SOI structures. The P-SSDT shows a excellent electrical properties like hole mobility and S/D series resistance.