The relative performance enhancement of strained-Si and buried channel p-MOS as a function of lithographic and effective gate lengths

The relative performance enhancement of strained-Si and buried channel p-MOS as a function of lithographic and effective gate lengths were investigated. Si- pMOS device results are presented from a standard 0.25 /spl mu/m CMOS process. A SiGe buried channel device on a SiGe virtual substrate is also investigated. With the different diffusion constants for Si and SiGe layers part of this enchancement may be related to differences in channel length. To remove any such effects, the effective gate length (L/sub eff/) was extracted using the shift and ratio technique and performance improvements have been compared for both lithographic gate length (L/sub g/) and effective gate length (L/sub eff/).