A Block Interconnection Algorithm for Hierarchical Layout System

A block interconnection algorithm for a general cell VLSI is described, which consists of a number of procedures such as a global router with signal delays taken into account, a router for power and ground, a block positioning scheme to minimize the chip size, a channel construction scheme with the use of L-shaped channels, and a grid-free channel router. The algorithm has been employed in a layout design system SMILE for general cell VLSI's for more than one year. Some of the experimental results are also shown.