New method for temperature-dependent thermal resistance and capacitance accurate extraction in high-voltage DMOS transistors

This work reports on the self-heating-effect (SHE) characterization of high-voltage (HV) DMOSFETs and a simple yet accurate extraction methodology of the equivalent thermal impedance of the device (thermal resistance, R/sub TH/, and capacitance, C/sub TH/). Systematic pulsed-gate experiments are used to study the influence of pulse duration and duty factor on device SHE and optimal extraction conditions. It is found that in 100 V DMOSFETs, the SHE is cancelled by using pulses with duration shorter than 2 /spl mu/s and duty factors lower than 1:100. The new extraction method uses dedicated extraction plots exploiting the gradual canceling of SHE with pulse duration and a new analytical modeling including the temperature dependence of RTH, is validated. For the first time, we report on the temperature dependence of RTH, from 25/spl deg/C up to 150/spl deg/C, in both saturation and quasi-saturation regions of DMOS, which is shown to be a quasi-linear yet significant function of the device internal temperature. Moreover, another new result is a power low-dependent thermal capacitance, as suggested by our experiments. Finally, SPICE simulations are used to validate the proposed method, and, demonstrate that a thermal-dependent thermal resistance model is highly critical for accurate advanced simulation of HV DMOS ICs.