Impact of gate-to-source/drain overlap length on 80-nm CMOS circuit performance

In this paper, we perform rigorous mixed-mode simulations on two-stage inverter circuit and sample-hold circuits, representative of digital, and analog applications, respectively. The impact of gate-source/drain overlap length on circuit performance in an 80-nm CMOS circuit is evaluated by varying the overlap length between 0 to 20 nm, while keeping the subthreshold leakage current constraint at 1, 10, and 100 nA//spl mu/m. Process variations about the nominal overlap length have also been accounted for. The stage delay and switch error are used as the performance metrics. The lateral peak electric field is used as the metric for the hot carrier reliability. It is demonstrated that the overlap length should be made as small as possible, in spite of the increase in series resistance, in order to get the best circuit performance and reliability.