Analysis and design of level-converting flip-flops for dual-V/sub dd//V/sub th/ integrated circuits

This paper investigates the performance and energy consumption of six fully static CMOS edge-triggered level-converting flip-flops (LCFFs). These flip-flops provide the necessary voltage level conversion from a lower to a higher supply without incurring leakage currents in dual-V/sub dd/ systems while maintaining good speed. In particular, we propose two novel designs and extend two previous non-level-converting flip-flops to intrinsically perform level conversion. In addition, the robustness of the newly proposed LCFFs is investigated based on worst-case process corners as well as power supply noise. Results show delay improvement of up to 50% and energy-delay product reductions of 15-50% compared to a conventional level-converting master-slave flip-flop.