A highly efficient modeling style for heterogeneous bus architectures

The ever increasing complexity and heterogeneity of modern systems-on-chip designs demands validation of the system performance as early as possible. The on-chip bus architectures play an important role to meet the design performance. Today many heterogeneous on-chip bus architectures are defined to address the design exploration. In this paper we introduce an efficient modeling style of heterogeneous bus architectures at high levels of abstraction. We capture different bus architectures by using a generic, parametrizable bus model, which captures performance issues without significant loss of accuracy. Our modeling style is based on the system C language, a special channel library and attached coding style. The combination provides the ground layer for the efficient and fast simulation, which in turn enables the validation of the functionality and performance of the system at high abstraction levels. The approach has been successfully used from defining the executable specification at the functional level to the architecture explorations with HW/SW integration for an IPv4 router with quality of support, design example.