xICU - in interrupt control unit for a configurable DSP core

Increasing complexity of SoC applications leads to a strong demand on powerful software programmable embedded cores. Low-cost applications do not allow adding more than one core to the application. Depending on the application a DSP or a microcontroller is used. Therefore DSP cores have to handle interrupts typically served by microcontroller sub-systems also with low latency and small overhead concerning cycle count and code density. This paper describes the architecture of an ICU (interrupt control unit) for a configurable DSP core. The main architectural features of the ICU can be configured to reduce the consumed silicon area to an application specific optimum. Priority morphing is introduced to enable the control of the execution order of pending interrupt sources during run-time and to prevent the loss of interrupt information. A smooth integration into the program sequencer allows short interrupt latency and low overhead for serving ISRs (interrupt service routines). xICU is a part of a configurable DSP core.